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請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/10126
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| 題名: | The Implementation and Analysis of an All-digital Phase-locked Loop |
| 作者: | Chen, Po-Yueh;Su, Hung-Lung |
| 貢獻者: | 資訊工程學系 |
| 關鍵詞: | All-digital phase-locked loop (ADPLL);Digitally Controlled oscillator (DCO);Phase and frequency detector (PFD) |
| 日期: | 2006-05
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| 上傳時間: | 2012-05-03T09:14:52Z
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| 出版者: | 國立高雄海洋科技大學 |
| 摘要: | An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in eep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time. This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity phase and frequency detector (PFD). Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications. |
| 關聯: | 第四屆微電子技術發展與應用研討會, 國立高雄海洋科技大學, 2009年5月19日 |
| 顯示於類別: | [資訊工程學系] 會議論文
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| 2050401016003.pdf | 46Kb | Adobe PDF | 661 | 檢視/開啟 |
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