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請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/10256

題名: Hardware Implementation for a Genetic Algorithm
作者: Chen, Pei-Yin;Chen, Ren-Der;Chang, Yu-Pin;Shieh, Leang-San;Malki, Heidar A.
貢獻者: 資訊工程學系
關鍵詞: Field-programmable gate array (FPGA);Genetic algorithm (GA);Intellectual property (IP);Software system;Verilog
日期: 2008-04
上傳時間: 2012-05-22T06:12:25Z
出版者: Institute of Electrical and Electronics Engineers
摘要: A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.
關聯: IEEE Trans. Instrumentation and Measurement, 57(4): 699-705
顯示於類別:[資訊工程學系] 期刊論文

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