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http://ir.ncue.edu.tw/ir/handle/987654321/10258
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| Title: | Design of a dynamic pipelined architecture for fuzzy color correction |
| Authors: | Jou, Jer-Min;Kuang, Shiann-Rong;Shiau, Yeu-Horng;Chen, Ren-Der |
| Contributors: | 資訊工程學系 |
| Keywords: | Color correction;Dynamic pipeline;Fuzzy |
| Date: | 2002-12
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| Issue Date: | 2012-05-22T06:12:30Z
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| Publisher: | Institute of Electrical and Electronics Engineers |
| Abstract: | Color correction, which nonlinearly converts the color coordinates of an input device such as the scanner and digital camera into that of an output device such as the color laser printer, is important for multimedia applications. In this work, we present a novel dynamic pipelined VLSI architecture for the fuzzy color correction algorithm (FCC) proposed by Jou et al. (see IEEE Trans. Circuits Syst. I, vol.46, p.773-775, June 1998) to meet the speed requirement of time-critical applications. To promote the performance, the presented architecture is dynamically pipelined with unfixed or run-time determined latencies (or data initiation intervals) and the speculation technique is also applied, then the problems of arduous pipelining, due to the variant execution time of each iteration and slower executing of FCC are solved efficiently. As for data path design, a systematic design methodology of high-level synthesis is used. As a result, a significant (about 2 times) speedup of the dynamic pipelined architecture with a slight hardware overhead relative to the sequential one has been achieved. |
| Relation: | IEEE Trans. Very Large Scale Integration (VLSI) Systems, 10(6): 924-929 |
| Appears in Collections: | [資訊工程學系] 期刊論文
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