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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/10260

Title: Dynamic pipeline design of an adaptive binary arithmetic coder
Authors: Kuang, Shiann-Rong;Jou, Jer-Min;Chen, Ren-Der;Shiau, Yeu-Horng
Contributors: 資訊工程學系
Keywords: Arithmetic coding;Data compression;Dynamic pipeline
Date: 2001-09
Issue Date: 2012-05-22T06:12:34Z
Publisher: Institute of Electrical and Electronics Engineers
Abstract: Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a lower-area but faster fixed-width multiplier are applied, which implement the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8-μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential realisation is achieved.
Relation: IEEE Trans. Circuits & Systems, Part II, 48(9): 813-825
Appears in Collections:[資訊工程學系] 期刊論文

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