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题名: Design of low-error fixed-width multipliers for DSP applications
作者: Jou, Jer-Min;Kuang, Shiann-Rong;Chen, Ren-Der
贡献者: 資訊工程學系
日期: 1999-06
上传时间: 2012-05-22T06:12:36Z
出版者: Institute of Electrical and Electronics Engineers
摘要: In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2 n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low error reduced-width multiplier with output bit-width between n- and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
關聯: IEEE Trans. Circuits & Systems, Part II, 46(6): 836-842
显示于类别:[資訊工程學系] 期刊論文


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