National Changhua University of Education Institutional Repository : Item 987654321/10261
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 6491/11663
造訪人次 : 25195005      線上人數 : 75
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜尋範圍 進階搜尋

請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/10261

題名: Design of low-error fixed-width multipliers for DSP applications
作者: Jou, Jer-Min;Kuang, Shiann-Rong;Chen, Ren-Der
貢獻者: 資訊工程學系
日期: 1999-06
上傳時間: 2012-05-22T06:12:36Z
出版者: Institute of Electrical and Electronics Engineers
摘要: In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and two's-complement parallel multipliers for digital signal processing applications are presented. Given two n-bit inputs, the fixed-width multipliers generate n-bit (instead of 2 n-bit) products with low product error, but use only about half the area and less delay when compared with a standard parallel multiplier. In them, cost-effective carry-generating circuits are designed, respectively, to make the products generated more accurately and quickly. Applying the same approach, a low error reduced-width multiplier with output bit-width between n- and 2n has also been designed. Experimental results show that the proposed fixed-width and reduced-width multipliers have lower error than all other fixed-width multipliers and are still cost effective. Due to these properties, they are very suitable for use in many multimedia and digital signal processing applications such as digital filtering, arithmetic coding, wavelet transformation, echo cancellation, etc.
關聯: IEEE Trans. Circuits & Systems, Part II, 46(6): 836-842
顯示於類別:[資訊工程學系] 期刊論文

文件中的檔案:

檔案 大小格式瀏覽次數
index.html0KbHTML536檢視/開啟


在NCUEIR中所有的資料項目都受到原著作權保護.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回饋