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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/10263
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| Title: | Investigating the FIFO design styles based on the Balsa synthesis system |
| Authors: | Chen, Ren-Der;Lee, Che-An;Hsieh, Pei-Hua |
| Contributors: | 資訊工程學系 |
| Keywords: | Asynchronous;Balsa;FIFO |
| Date: | 2011-12
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| Issue Date: | 2012-05-22T06:13:16Z
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| Abstract: | In this paper, three asynchronous FIFO design styles, linear, square, and cubic, are investigated based on the Balsa synthesis system. These styles are designed with the key difference being the path by which data travels through the FIFO. The design with shorter path should result in lower latency and higher throughput, but will require more complicated control. All the FIFOs are designed using the Balsa language, and the area cost and simulation time are compared for each FIFO with varying sizes. A tool is also presented for automatic generation of Balsa code for each FIFO. |
| Relation: | 2011 International Symposium on Integrated Circuits, ISIC 2011, Singapore, December 12-14, 2011:176-179 |
| Appears in Collections: | [資訊工程學系] 會議論文
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