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| 題名: | Comparative design of floating-point arithmetic units using the Balsa synthesis system |
| 作者: | Chen, Ren-Der;Chou, Yu-Cheng;Liu, Wan-Chen |
| 貢獻者: | 資訊工程學系 |
| 關鍵詞: | Asynchronous;Balsa;Floating-point adder/subtractor;Modified Booth algorithm;Multiplier |
| 日期: | 2011-12
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| 上傳時間: | 2012-05-22T06:13:18Z
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| 摘要: | In this paper, the asynchronous floating-point arithmetic units consisting of adders/subtractors and multipliers are designed and compared based on the Balsa synthesis system. For the critical mantissa multiplication in the multiplier, the modified Booth algorithm (radix 2, 4, and 8) is adopted. A pipelined design of the multiplier is also presented to increase performance. Since the Balsa language is compiled using syntax-directed translation, for the two different if statements and one case statement supported by Balsa, three different description styles have been made for each design. It can be seen from the experimental results how the style affects the area cost and simulation time of the resulting circuit. This gives us a guide to choose appropriate control statements for designing Balsa-based asynchronous circuits. |
| 關聯: | 2011 International Symposium on Integrated Circuits, ISIC 2011, Singapore, December 12-14, 2011:172-175 |
| 顯示於類別: | [資訊工程學系] 會議論文
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