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| 題名: | Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme |
| 作者: | Chang, Meng-chou;Lai, Feipei;Shang, Rung-ji |
| 貢獻者: | 電子工程學系 |
| 日期: | 1992-12
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| 上傳時間: | 2012-05-22T06:46:04Z
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| 出版者: | IEEE Computer Society Press Los Alamitos |
| 摘要: | This paper proposes a new microarchitecture, called
IAS-S, which takes advantage of the Conjugate Register
File (CRF) scheme to support speculative execution,
such as multi-level boosting and multi-way
branch, without incurring excessive hardware overhead.
A software technique which integrates register
allocation and instruction scheduling has been developed
to exploit the conjugate register file. The
scheduling-conflict graphis built before the starting of
register allocation so that the ability of the instruction
scheduler to optimize the instruction sequence
will not be severely restricted by the reuse of registers. |
| 關聯: | 25th International Symposium on Microarchitecture (sponsored by IEEE and ACM), 1992年12月1-4日: 29-32 |
| 顯示於類別: | [電子工程學系] 會議論文
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