Loading...
|
Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/10376
|
| Title: | Design of an Asynchronous Pipelined Processor |
| Authors: | Chang, Meng-chou;Shiau, Da-Sen |
| Contributors: | 電子工程學系 |
| Date: | 2008-05
|
| Issue Date: | 2012-05-22T06:47:29Z
|
| Publisher: | IEEE |
| Abstract: | Asynchronous circuits have the potential advantages
of low power consumption, high operating speed, low electromagnetic
emission, no clock skew problem, and robustness
towards variations in temperature, supply voltage and
fabrication process parameters. This paper introduces the
design of an asynchronous pipelined processor, called
AsynRISC, which is implemented by using the asynchronous
hardware description language Balsa. Since asynchronous
logic adopts distributed control scheme, the traditional
methods for handling hazards in synchronous processors can
not be directly applied to asynchronous processors. In this
paper, the methods for dealing with data hazards and control
hazards in AsynRISC are discussed. |
| Relation: | 2008 International Conference on Communications, Circuits and System (ICCCAS 2008), May 25-27, 2008: 1093-1096 |
| Appears in Collections: | [電子工程學系] 會議論文
|
Files in This Item:
| File |
Size | Format | |
|---|
| index.html | 0Kb | HTML | 546 | View/Open |
|
All items in NCUEIR are protected by copyright, with all rights reserved.
|
