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題名: | Design of an Asynchronous Pipelined Processor |
作者: | Chang, Meng-chou;Shiau, Da-Sen |
貢獻者: | 電子工程學系 |
日期: | 2008-05
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上傳時間: | 2012-05-22T06:47:29Z
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出版者: | IEEE |
摘要: | Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed. |
關聯: | 2008 International Conference on Communications, Circuits and System (ICCCAS 2008), May 25-27, 2008: 1093-1096 |
顯示於類別: | [電子工程學系] 會議論文
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