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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/10379

Title: 結合非同步技術與絕熱邏輯的低功率電路設計
Authors: 張孟洲;蔡佳昌
Contributors: 電子工程學系
Keywords: 絕熱式邏輯;非同步電路;低功率;交握式傳輸協定
Adiabatic logic;Asynchronous circuit;Low power;Handshake protocol
Date: 2009-05
Issue Date: 2012-05-22T06:47:32Z
Publisher: 國立成功大學
Abstract: 本論文提出一個新的低功率電路的設計技術,此技術結合了「非同步電路」與「絕熱邏輯」這兩種低功率技術的優點,稱為「交握式準絕熱邏輯」(Handshaking Quasi-Adiabatic Logic;HQAL)。HQAL採用dual-rail的資料編碼方式,並且採用非同步交握式方式來傳送資料。因此,HQAL具有非同步電路的優點:沒有時脈歪斜問題、沒有因clock tree所導致的功率消耗,並且在沒有資料輸入時,沒有動態功率消耗。HQAL的邏輯閘的電源是由「交握控制鏈」(Handshake Control Chain)所控制,當HQAL邏輯閘沒有輸入資料時,它得不到電源;只有當HQAL邏輯閘有輸入資料時,它才獲得電源,並且以跟絕熱邏輯相似的方式運作,而達到低功率消耗。利用交握控制鏈,HQAL避免了發生在傳統非同步絕熱邏輯(Asynchronous Adiabatic Logic;AAL)電路裡data token被蓋過的問題。模擬結果顯示8位元管線Sklansky加法器的HQAL實現方式比傳統CMOS實現方式在輸入資料率為700MHZ的情況下節省了33.1%的功率消耗,在輸入資料率為10MHZ的情況下節省了72.5%的功率消耗。
This paper proposes a novel low-power logic circuit, called handshaking quasi-adiabatic logic (HQAL), which combines the advantages of asynchronous circuits and adiabatic logics. The HQAL logics adopt dual-rail encoding, and employ handshaking to transfer data between the adjacent modules. Hence, HQAL has the advantages of asynchronous circuits: no clock skew problem, no power dissipation due to the clock tree, and no dynamic power dissipation when there are no input data. The power line of the HQAL logic gates is controlled by the handshake control chain (HCC). A HQAL logic gate is not supplied with power when it has no input data. Only when a HQAL gate has acquired its input data, it can gain the power and then operate in a way similar to the adiabatic logic. Hence, the HQAL logic can achieve low power dissipation. With the handshake control chain, the HQAL circuit can avoid the problem of data token overriding, which may occur in conventional asynchronous adiabatic logic (AAL) circuits. Simulation results showed that the HQAL implementation of a pipelined Sklansky adder can achieve 33.1% reduction in power dissipation, compared to the CMOS implementation, for a data rate of 700 MHz and 72.5% reduction in power dissipation for a data rate of 10 MHz.
Relation: 2009數位生活科技研討會:人本智慧生活科技論文集, 國立成功大學, 2009年5月28-29日
Appears in Collections:[電子工程學系] 會議論文

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