資料載入中.....
|
請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/10889
|
| 題名: | The New Architecture of Radix-4 Chinese Abacus Adder |
| 作者: | Yi, S.-C.;Lee, K.-T.;Chen, Jin-Jia;Lin, C.-H.;Wang, C.-C.;Hsieh, C.-F.;Lu, C.-Y. |
| 貢獻者: | 電機工程學系 |
| 日期: | 2006-05
|
| 上傳時間: | 2012-06-04T09:11:28Z
|
| 出版者: | IEEE Computer Society |
| 摘要: | In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35�m, 0.25�m, and 0.18�m technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35�m, 0.25�m, and 0.18�m technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder. |
| 關聯: | 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006, Singapore, May 17-20, 2006: 12 |
| 顯示於類別: | [電機工程學系] 會議論文
|
文件中的檔案:
| 檔案 |
大小 | 格式 | 瀏覽次數 |
|---|
| index.html | 0Kb | HTML | 658 | 檢視/開啟 |
|
在NCUEIR中所有的資料項目都受到原著作權保護.
|
