National Changhua University of Education Institutional Repository : Item 987654321/10889
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 6507/11669
造访人次 : 30009768      在线人数 : 380
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 进阶搜寻

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/10889

题名: The New Architecture of Radix-4 Chinese Abacus Adder
作者: Yi, S.-C.;Lee, K.-T.;Chen, Jin-Jia;Lin, C.-H.;Wang, C.-C.;Hsieh, C.-F.;Lu, C.-Y.
贡献者: 電機工程學系
日期: 2006-05
上传时间: 2012-06-04T09:11:28Z
出版者: IEEE Computer Society
摘要: In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35�m, 0.25�m, and 0.18�m technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35�m, 0.25�m, and 0.18�m technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.
關聯: 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006, Singapore, May 17-20, 2006: 12
显示于类别:[電機工程學系] 會議論文

文件中的档案:

档案 大小格式浏览次数
index.html0KbHTML658检视/开启


在NCUEIR中所有的数据项都受到原著作权保护.

 

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈