資料載入中.....
|
請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/11657
|
題名: | Combining the Folding and Testing for Programmable Logic Arrays |
作者: | Wei, Kai-Cheng;Liu, B. D. |
貢獻者: | 資訊工程系 |
日期: | 1994
|
上傳時間: | 2012-06-18T02:34:00Z
|
出版者: | World Scientific Publishing |
摘要: | Different from the previous techniques which treated the folding and testing for PLAs as separate problems, this paper presents a new approach to combine the bipartite folding and testing for PLA’s in the same procedure. Fewer silicon area than other existing comparable techniques is required to make the PLA testable. Experimental results show that this technique can reduce chip area, test length, test storage and time complexity. |
關聯: | Journal of Circuits systems and Computers, 4(3): 305-317 |
顯示於類別: | [資訊工程學系] 期刊論文
|
文件中的檔案:
檔案 |
大小 | 格式 | 瀏覽次數 |
2050400610001.pdf | 69Kb | Adobe PDF | 477 | 檢視/開啟 |
|
在NCUEIR中所有的資料項目都受到原著作權保護.
|