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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/11657

Title: Combining the Folding and Testing for Programmable Logic Arrays
Authors: Wei, Kai-Cheng;Liu, B. D.
Contributors: 資訊工程系
Date: 1994
Issue Date: 2012-06-18T02:34:00Z
Publisher: World Scientific Publishing
Abstract: Different from the previous techniques which treated the folding and testing for PLAs as separate problems, this paper presents a new approach to combine the bipartite folding and testing for PLA’s in the same procedure. Fewer silicon area than other existing comparable techniques is required to make the PLA testable. Experimental results show that this technique can reduce chip area, test length, test storage and time complexity.
Relation: Journal of Circuits systems and Computers, 4(3): 305-317
Appears in Collections:[資訊工程學系] 期刊論文

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