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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/11658
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| Title: | Low Overhead Design for Programmable Logic Array with Testability |
| Authors: | Wei, Kai-Cheng;Sheu, J. J.;Liu, B. D. |
| Contributors: | 資訊工程系 |
| Date: | 1994
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| Issue Date: | 2012-06-18T02:34:14Z
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| Publisher: | Taylor |
| Abstract: | A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this design is significantly less than those of previous methods. |
| Relation: | Int. J. Electronics, 77(2): 241-250 |
| Appears in Collections: | [資訊工程學系] 期刊論文
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Files in This Item:
| File |
Size | Format | |
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| 2050400610002.pdf | 5Kb | Adobe PDF | 412 | View/Open |
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