National Changhua University of Education Institutional Repository : Item 987654321/11660
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题名: Low Test-Application Time Method for EEPLA testing
作者: Wei, Kai-Cheng;Liu, B. D.;Tang, J. J.
贡献者: 資訊工程系
日期: 1997-01
上传时间: 2012-06-18T02:34:29Z
出版者: Institute of Electrical Engineers
摘要: An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.
關聯: EE Proc. Computer and Digital Techniques, 144(1): 39-42
显示于类别:[資訊工程學系] 期刊論文

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