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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/11665

Title: Using the charge recycling technique for low power PLA design
Authors: Xiao, C.-T.;Wei, Kai-Cheng
Contributors: 資訊工程系
Date: 2010-04
Issue Date: 2012-06-18T02:34:54Z
Publisher: IEEE
Abstract: This paper presents a new low-power charge-recycling dynamic programmable logic array (PLA). The charge recycling PLA reduces the power consumption in product lines by recycling the previously used charge. The proposed dynamic PLA, product lines swing voltage is lowered by the charge recycling circuit between on adjacent product lines. Power consumption in product lines can be reduced theoretically to half by the proposed charge-recycling techniques. The simulation results show that the proposed scheme reduces delay by 38.7%, power by 17.4% and total power delay product (PDP) by 49.4% compared to the conventional PLA in a 0.35μm CMOS process technology.
Relation: 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, April 26-29, 2010
Appears in Collections:[資訊工程學系] 會議論文

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