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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/14008

Title: 一個達到1.5dB-NF的高增益全積體化低雜訊放大器設計
A Design for a Fully Integrated High-Gain LNA with 1.5dB-NF
Authors: 陳勛祥;林愷
Contributors: 電子工程學系
Keywords: 互補式金屬氧化物半導體低雜訊放大器;無線;全積體化放大器;低雜訊;雜訊指數;1-dB壓縮點;三階截止點
CMOS LNA;RF;Wireless;Fully integrated amplifier;Low noise;Noise figure;1-dB compression;IP3
Date: 2004-06
Issue Date: 2012-09-10T02:38:50Z
Publisher: 大葉大學
Abstract: 本論文描述出一個適用於RF(radio frequency,射頻)無線應用的CMOS LNA(互補式金屬氧化物半導體低雜訊放大器),使用0.25μm製程來設計一個工作於2.5V並且適用於2.38GHz的頻段。本論文主要模擬的重點在於此LNA的輸出入阻抗匹配、隔絕度、功率增益、線性度以及功率消耗,經由調整LNA電路各個組成,來設計出LNA電路的最佳效能。由模擬結果顯示出此LNA電路具有功率增益20dB、雜訊指數1.5dB、三階截止點(IP3)為 -18dB、功率消耗為18.5mW以及優良的輸出輸入阻抗匹配。
A CMOS (complementary metal oxide semiconductor) low noise amplifier (LNA) suitable for radio frequency (RF) wireless applications is investigated in this study. A fully integrated 2.38-GHz CMOS LNA is implemented by using 0.25μm CMOS technology with a 2.5V power supply. The main simulation points are input/output impedance matching, isolation, power gain, linearity and power consumption. Through adjusting the component values of the LNA, the optimization can be determined. Simulation results show that the LNA is characterized by a power gain of 20dB, a noise figure of 1.5dB, an IP3 of -18dBm, a power dissipation of 18.5mW, and well-matched input/output.
Relation: 大葉學報, 13(1): 41-49
Appears in Collections:[電子工程學系] 期刊論文

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