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NCUEIR > College of Engineering > eedept > Periodical Articles > Item 987654321/14018

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/14018

Title:	Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
Authors:	Wu, Tsung-Yi;Lu, Liang-Ying
Contributors:	電子工程學系
Keywords:	Dual value logic;Leakage current;Pass-transistor logic gate;Standard cell;Transmission gate
Date:	2009
Issue Date:	2012-09-10T02:49:09Z
Publisher:	Oxford University Press
Abstract:	In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
Relation:	IEICE Transactions on Electronics, E92-C(4): 401-408
Appears in Collections:	[eedept] Periodical Articles

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