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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/14020

Title: 雙值邏輯與傳統邏輯閘合成器之研究(I)
Research on a Synthesizer of Dual Value Logic and Traditional Logic Gates (I)
Authors: 吳宗益
Contributors: 電子工程學系
Keywords: 標準元件庫;互補式金屬氧化半導體邏輯閘;雙值邏輯+閘;邏輯閘合成器
Standard-Cell Library;CMOS Logic Gate;Dual Value Logic+ (DVL+) Gate;Logic Gate Synthesizer
Date: 2010
Issue Date: 2012-09-10T02:52:42Z
Publisher: 行政院國家科學委員會
Abstract: 不管是使用全客製化或是標準元件的方法來設計電路,一個數位超大型積體電路都是由成千上萬的邏輯閘組合而成,因此如何提供適當的邏輯閘元件給電路設計者就顯得特別重要。對於使用標準元件設計方法的工程師而言,不同應用的電路設計可能會有不同標準元件庫的需求。但是基於成本考量,標準元件庫供應商是無法顧及每個客戶的需求,所以他們只能提供幾種通用的標準元件庫給所有客戶,除非客戶下了客製化標準元件庫之訂單。為了減少標準元件或特殊邏輯閘的開發成本,此計畫打算研發一個電晶體階層的邏輯閘合成器,該合成器能依使用者所提供的欲合成邏輯閘之布林函數以及合成條件限制,自動建構符合條件限制的該邏輯閘之SPICE 電路。我們要開發的邏輯閘合成器除了能合成傳統的互補式金屬氧化半導體(CMOS)邏輯閘外,還能合成我們所發明的雙值邏輯+(Dual Value Logic+)閘。之所以要提供合成雙值邏輯+閘之功能是因為對某些布林函數而言,雙值邏輯+閘的表現要比傳統CMOS 邏輯閘還好。為了在合理的時間內合成出最佳的邏輯閘之 SPICE 電路,合成器會依邏輯閘的複雜度採用合適的演算法,例如︰分枝界限(Branch and Bound)及模擬退火(Simulated Annealing)演算法。由於商用靜態時序分析(STA)軟體無法準確算出內含雙值邏輯+閘的電路,所以此計畫也會研究如何解決這個問題。
Both a full custom digital design and a standard-cell based design contain a huge number of logic gates if they are VLSI circuits. Therefore, how to support suitable logic gates for circuit designers is very important. For the engineers who use the standard-cell design methodology, their selections of standard-cell library types depend on the application types of the circuit designs. However, the providers of standard-cell libraries cannot satisfy each customer and give each customer a specific standard-cell library required by the customer. The reason is that the development of a standard-cell library is costly. Therefore the standard-cell library provider only can release few standard-cell libraries to all customers unless customers can order specific cell libraries. In order to reduce the development cost of standard cells or specific logic gates, the project plans to develop a logic gate synthesizer. The synthesizer can synthesize the SPICE circuit of a logic gate that is described by a Boolean function, and the synthesized circuit can meet the constraint given by a user. The synthesizer can synthesize not only traditional CMOS gates but also our proposed Dual Value Logic+ (DVL+) gates. The reason of why we plan to synthesize Dual Value Logic+ gates is that Dual Value Logic+ gates are better than traditional CMOS gates in implementing some specific Boolean functions. The synthesizer may use different algorithms (e.g. Branch and Bound Algorithm, Simulated Annealing Algorithm, etc.) for different input Boolean functions for synthesizing the better circuits under reasonable CPU times. We also study how to solve the problem that commercial static time analysis (STA) tools cannot correctly calculate the timing of a circuit that has DVL+ gates.
Relation: 國科會計畫, 計畫編號: NSC99-2221-E018-031; 研究期間: 9908-10007
Appears in Collections:[電子工程學系] 國科會計畫

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