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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/14025
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| Title: | IR Drop Reduction Via a Flip-Flop Resynthesis Technique |
| Authors: | Wu, Jiun-Kuan;Wu, Tsung-Yi;Lu, Liang-Ying;Chen, Kuang-Yao |
| Contributors: | 電子工程學系 |
| Date: | 2008-03
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| Issue Date: | 2012-09-10T02:55:51Z
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| Publisher: | Institute of Electrical and Electronics Engineers |
| Abstract: | Clock skew scheduling for peak current reduction is a conventional technique for solving IR-drop problem in physical design stage. In this paper, we propose two kinds of long delay flip-flops and a heuristic algorithm that is used to resynthesize flip-flops of a circuit. Because the switching times of flip-flops in the resynthesized circuit are staggered, the IR drop effect can be reduced. Unlike clock skew scheduling, our technique
not only can be used in physical design stage but also in logic design stage. The other advantages of our technique over the clock skew optimization technique are that our technique has less area overhead and has more opportunities to find a better result. |
| Relation: | 9th International Symposium on Quality Electronic Design, ISQED 2008, San Jose, CA, March 17-19, 2008: 78-83 |
| Appears in Collections: | [電子工程學系] 會議論文
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