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NCUEIR > College of Engineering > eedept > Proceedings > Item 987654321/14026

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/14026

Title:	Low-Leakage and Low-Power Implementation of High-Speed 65nm Logic Gates
Authors:	Wu, Tsung-Yi;Lu, Liang-Ying;Liang, Cheng-Hsun
Contributors:	電子工程學系
Date:	2008-12
Issue Date:	2012-09-10T02:55:55Z
Publisher:	Institute of Electrical and Electronics Engineers
Abstract:	In this paper, we propose novel transmissiongate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65nm CMOS gates, our proposed 65nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.
Relation:	2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, Hong Kong, December 8-10, 2008
Appears in Collections:	[eedept] Proceedings

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