English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 6507/11669
造訪人次 : 29618699      線上人數 : 269
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜尋範圍 進階搜尋

請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/14028

題名: A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers
作者: Wu, Tsung-Yi;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun;Lin, How-Rern
貢獻者: 電子工程學系
日期: 2009-05
上傳時間: 2012-09-10T02:56:00Z
出版者: Institute of Electrical and Electronics Engineers
摘要: In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. The goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%.
關聯: The 13th IEEE International Symposium on Consumer Electronics, ISCE 2009, Kyoto, May 25-28, 2009: 128-129
顯示於類別:[電子工程學系] 會議論文

文件中的檔案:

檔案 大小格式瀏覽次數
index.html0KbHTML565檢視/開啟


在NCUEIR中所有的資料項目都受到原著作權保護.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回饋