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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/14028
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| Title: | A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers |
| Authors: | Wu, Tsung-Yi;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun;Lin, How-Rern |
| Contributors: | 電子工程學系 |
| Date: | 2009-05
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| Issue Date: | 2012-09-10T02:56:00Z
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| Publisher: | Institute of Electrical and Electronics Engineers |
| Abstract: | In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme of mixed positive and negative triggering edges rather than one of pure positive (negative) triggering edges. In this paper, we propose a software tool that can assign either a rising triggering edge or a falling triggering edge to each clock of each block of a given system-level design. The goal of the clock-triggering-edge assignment is to reduce the peak current of the design. Experimental results show that our tool can reduce the peak current up to 45.3% and reduce the power pad count up to 40.0%. |
| Relation: | The 13th IEEE International Symposium on Consumer Electronics, ISCE 2009, Kyoto, May 25-28, 2009: 128-129 |
| Appears in Collections: | [電子工程學系] 會議論文
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