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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/14029
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| Title: | Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs |
| Authors: | Wu, Tsung-Yi;Kao, Tzi-Wei;Huang, Shi-Yi;Li, Tai-Lun;Lin, How-Rern |
| Contributors: | 電子工程學系 |
| Date: | 2010-01
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| Issue Date: | 2012-09-10T02:56:04Z
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| Publisher: | IEEE |
| Abstract: | In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggeringedge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core or block of a given IP-based SoC design. The goal of the algorithms is to reduce the peak current of the design.
Experimental results show that our algorithms can reduce peak currents up to 56.3%. |
| Relation: | 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, January 18-21, 2010: 444-449 |
| Appears in Collections: | [電子工程學系] 會議論文
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