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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/16444
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| Title: | Hardware Implementation of a High-Speed (32, 24, 4) RS Decoder |
| Authors: | Chen, Tung-Chou;Tasi, Ming-Hsi |
| Contributors: | 電子工程學系 |
| Keywords: | Reed-Solomon codes;Step-by-step;Decoder;FPGA;High-speed |
| Date: | 2007-12
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| Issue Date: | 2013-05-06T03:50:24Z
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| Publisher: | 中華大學工學院 |
| Abstract: | Reed-Solomon (RS) code is one of the most frequently employed forward-error-correcting (FEC) codes in digital transmission and storage systems. A well-known decoding method, the step-by-step algorithm, can decode the RS code in a symbol-by-symbol manner with low latency delay. This method can directly determine whether the received code symbol is erroneous or not and immediately find the corresponding error value without requiring of finding the error location polynomial. Based on a modified step-by-step RS decoding algorithm, a high-speed pipelined (32, 24, 4) RS decoder is implemented for Gbits/sec data transmission. |
| Relation: | Chung Hua Journal of Science and Engineering, 5(4): 21-27 |
| Appears in Collections: | [電子工程學系] 期刊論文
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