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NCUEIR > College of Science > Graduate Institute of Photonics Technologies > NSC Projects > Item 987654321/17759

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/17759

Title:	臨界特性調變技術於軟性有機電子應用之研究 The Study on the Threshold Characteristics Modulation Technology for the Flexible Organic Electronics
Authors:	王右武;陳建亨
Contributors:	光電科技研究所
Date:	2009
Issue Date:	2013-12-30T09:44:50Z
Publisher:	行政院國家科學委員會
Abstract:	本計畫將分成三年度執行，第一年，著重在對單一元件的控制與處理，尤其是臨界特性調變技術的開發，本年度可分為兩部分(a)我們預計使用奈米壓印熱轉換法進行有機與有機材料間的摻雜，或者是有機與染料分子間的摻雜，研究摻雜對電晶體特性的調變，包括了通道區的調變，與接觸電極區的調變。(b)其次我們將針對有機半導體薄膜與介電層間進行介面的控制，分別使用電漿處理進行表面改質，與自組裝分子層進行前處理，雖然這方面國內外研究做了許多，但是對與介電層與有機半導體間所產生的各種問題(例如Interface Dipole)卻未有妥善的解釋與解決方案，而我們預計使用駐極體(Electrets)材質，在表面提供一恆定的靜電壓，或可消除某部分介面效應，增加對起始電壓的控制能力。第二年，則著重將開發出之新臨界特性調變技術應用於邏輯閘與小型的陣列 (Array)，製作符合高驅動速度之電路基本單元。同樣分為兩部分，(a)首先對於電晶體臨界狀態的控制，必須完成同一製程中，可分區分別進行製程，以得到不同臨界特性的電晶體。我們計畫使用選擇性自組裝分子層，在處理過的表層上製作不同的介面，藉以取得不同的電晶體特性，並搭配輔助的半導體層摻雜技術，以進行更精確的控制。以之製作電子電路邏輯單元(AND、OR、振盪器)。(b)使用第一年的駐極體(Electrets)壓電薄膜，搭配對臨界電壓的偵測，製作32×32 壓電式感測器陣列，可用於Touch Panel 領域。製作之陣列感測器靈敏度高與分辨率強，主要取決於壓電膜的靜電壓隨外界壓力的變化曲線，與電晶體的臨界特性改變。第三年，將延續第二年的計畫，進行使用OTFT 製作之有機電子電路，同樣分成兩個部分，(a)第一、二年計畫執行後，我們將掌握了對電晶體臨界特性調變的基礎製程能力，因此將進一步測試有機電子的界線，有機電子受限於載子遷移率與元件面積，導致驅動速度慢與寄生效應大，我們將嘗試將訊號疊加，製作出類似倍頻的效果，增加其驅動能力。(b)多層有機立體元件之製作，VLSI 領域中隨製程縮小與連接線阻抗延遲效應，因此TSV(Through Silicon VIA)正被如火如荼的研究，對OTFT 而言，使用光阻性介電層與自組裝分子層則可較容易的實現3D 電路的多層架構，但同樣伴隨著眾多問題，本計畫的最後將嘗試這方面的技術研究，為有機電子的後續發展鋪路。 This project is a 3 years program. In the first year, the investigation would be focused on the fine tune technology of the organic transistor, especially on the threshold characteristics tuning technology. The study is divided into two correlated parts, (a) the doping process skill through nano-imprint thermal transfer method, and (b) the modulation of threshold characteristics through electrets layers and self-assemble layers. A successful fine tune process would lower down the threshold voltage and sub-threshold slop of the OTFT. In the second year, we focus on the fabrication of (a) the logic gates by applying the threshold tuning technology of the first year, and (b) a tunable 32�32 pressure-sensitive OTFT array with the electrets layer studied at the first year. That could be applied in the field of the touch panel. We would try to realize the organic integrated circuits or array. There are more requirements (such as uniformity, geometry) need to be take into account. In the third year, (a) we try to modify the structure of the organic logic gates to raise its operation frequency. We propose a circuit similar to the double frequency circuit design and seriously modify the device characteristics to optimize the circuit performance. (b) since the organic electronics suffer from its low driving ability, we suppose to realize a high density organic integrated circuits through 3D structure to shorten its connector path. Therefore, we could increase its device density and increase its driving speed.
Relation:	國科會計畫, 計畫編號: NSC98-2221-E018-017; 研究期間: 9808-9907
Appears in Collections:	[Graduate Institute of Photonics Technologies] NSC Projects

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