Loading...
|
Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/19081
|
| Title: | BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for Cmos Bridging Faults |
| Authors: | Lee, Kuen-Jong;Tang, Jing-Jou;Huang, Tsung-Chu |
| Contributors: | 電子工程學系 |
| Keywords: | Design;Experimentation;Reliability |
| Date: | 1999-04
|
| Issue Date: | 2014-10-27T08:06:16Z
|
| Publisher: | ACM |
| Abstract: | This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required. |
| Relation: | ACM Transactions on Design Automation of Electronic Systems, 4(2): 194-218 |
| Appears in Collections: | [電子工程學系] 期刊論文
|
Files in This Item:
| File |
Size | Format | |
|---|
| index.html | 0Kb | HTML | 651 | View/Open |
|
All items in NCUEIR are protected by copyright, with all rights reserved.
|
