資料載入中.....
|
請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/19081
|
| 題名: | BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for Cmos Bridging Faults |
| 作者: | Lee, Kuen-Jong;Tang, Jing-Jou;Huang, Tsung-Chu |
| 貢獻者: | 電子工程學系 |
| 關鍵詞: | Design;Experimentation;Reliability |
| 日期: | 1999-04
|
| 上傳時間: | 2014-10-27T08:06:16Z
|
| 出版者: | ACM |
| 摘要: | This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employing IDOQ testing can be achieved with only logic monitoring required. |
| 關聯: | ACM Transactions on Design Automation of Electronic Systems, 4(2): 194-218 |
| 顯示於類別: | [電子工程學系] 期刊論文
|
文件中的檔案:
| 檔案 |
大小 | 格式 | 瀏覽次數 |
|---|
| index.html | 0Kb | HTML | 868 | 檢視/開啟 |
|
在NCUEIR中所有的資料項目都受到原著作權保護.
|
