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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19083

Title: Reduction of Power Consumption in Scan-based Circuits During Test Application by an Input Control Technique
Authors: Huang, Tsung-Chu;Lee, Kuen-Jong
Contributors: 電子工程學系 
Keywords: ATPG;Full-scan;Low-power testing;Power minimization;VLSI testing
Date: 2001-07
Issue Date: 2014-10-27T08:06:19Z
Publisher: IEEE
Abstract: This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to identify an input control pattern (CP) for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated. A D-algorithm-like CP generator is developed to generate the CP. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.37% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.
Relation: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(7): 911-917
Appears in Collections:[電子工程學系] 期刊論文

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