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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/19084
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| Title: | An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application |
| Authors: | Lee, Kuen-Jong;Huang, Tsung-Chu |
| Contributors: | 電子工程學系 |
| Keywords: | Interleaving scan;Multiple scan chains;Peak power reduction;Test power reduction |
| Date: | 2002-12
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| Issue Date: | 2014-10-27T08:06:20Z
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| Publisher: | Kluwer Academic Publishers |
| Abstract: | This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed. |
| Relation: | Journal of Electronic Testing: Theory and Applications (JETTA), 18(6): 627-636 |
| Appears in Collections: | [電子工程學系] 期刊論文
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