English  |  正體中文  |  简体中文  |  Items with full text/Total items : 6469/11641
Visitors : 18523351      Online Users : 51
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search
LoginUploadHelpAboutAdminister

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19084

Title: An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application
Authors: Lee, Kuen-Jong;Huang, Tsung-Chu
Contributors: 電子工程學系 
Keywords: Interleaving scan;Multiple scan chains;Peak power reduction;Test power reduction
Date: 2002-12
Issue Date: 2014-10-27T08:06:20Z
Publisher: Kluwer Academic Publishers
Abstract: This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.
Relation: Journal of Electronic Testing: Theory and Applications (JETTA), 18(6): 627-636
Appears in Collections:[電子工程學系] 期刊論文

Files in This Item:

File SizeFormat
index.html0KbHTML287View/Open


All items in NCUEIR are protected by copyright, with all rights reserved.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback