資料載入中.....
|
請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/19084
|
| 題名: | An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application |
| 作者: | Lee, Kuen-Jong;Huang, Tsung-Chu |
| 貢獻者: | 電子工程學系 |
| 關鍵詞: | Interleaving scan;Multiple scan chains;Peak power reduction;Test power reduction |
| 日期: | 2002-12
|
| 上傳時間: | 2014-10-27T08:06:20Z
|
| 出版者: | Kluwer Academic Publishers |
| 摘要: | This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed. |
| 關聯: | Journal of Electronic Testing: Theory and Applications (JETTA), 18(6): 627-636 |
| 顯示於類別: | [電子工程學系] 期刊論文
|
文件中的檔案:
| 檔案 |
大小 | 格式 | 瀏覽次數 |
|---|
| index.html | 0Kb | HTML | 486 | 檢視/開啟 |
|
在NCUEIR中所有的資料項目都受到原著作權保護.
|
