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請使用永久網址來引用或連結此文件:
http://ir.ncue.edu.tw/ir/handle/987654321/19088
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| 題名: | High-yield Performance-efficient Redundancy Analysis for 2D Memory |
| 作者: | Huang, Tsung-Chu |
| 貢獻者: | 電子工程學系 |
| 關鍵詞: | Cluster faults;Fault tollerant;Hypercube;Memory repairing;Redundancy analysis;Remapping architecture |
| 日期: | 2011-08
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| 上傳時間: | 2014-10-27T08:06:24Z
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| 出版者: | Springer |
| 摘要: | High-yield performance-efficient remapping architecture, repairing algorithms and redundancy analysis (HYPERA) are proposed for 2D memory. The proposed hypercube-based memory repair architecture consists of spare row-like subcubes with a modified ternary CAM with an address concentrator and a parallel sorter-like address concentrator. Generally, for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work. |
| 關聯: | Science China Information Sciences, 54(8): 1663-1676 |
| 顯示於類別: | [電子工程學系] 期刊論文
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| 2050300910001.pdf | 25Kb | Adobe PDF | 396 | 檢視/開啟 |
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