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http://ir.ncue.edu.tw/ir/handle/987654321/19090
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| 題名: | 整合低電壓內建電流測試與即時低功率測試排程控制架構之研究
An On-Line Power-Constrained Scheduling Controller Combined with Low-Voltage Built-In Current Sensors for Deep-Submicron SOC Testing |
| 作者: | 黃宗柱 |
| 貢獻者: | 電子工程學系 |
| 關鍵詞: | Test controller;Low power design;Low power testing;IDDQ test;BICS;Power management;Test scheduling
測試控制器;低功率設計;低功率測試;靜態電流測試法;功率管理;測試排程 |
| 日期: | 2002
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| 上傳時間: | 2014-10-27T08:06:43Z
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| 出版者: | 行政院國家科學委員會 |
| 摘要: | In this project, we have followed some existing work to design a low-voltage low-power build-in current sensor for a hybrid scheme of BIST scheduling and monitoring for thermal and power constrained concurrent SOC test. Owing to increasing transistor density and operating speed in the SOC era, the reliability and power dissipation become two significant issues during test. To integrate many cores in a chip, deep submicron processes are required. This causes the IDDQ testing need solutions to survive, in which low-voltage design is an effective approach. On the other hand, to reduce the test time in SOC testing, concurrent test is urgent. This results in the power dissipation issue get more and more serious. We thus first develop a low voltage BICS using the forward biasing technique and the concept of using alternative stages with p- and n-MOS inputs. The current sensing transistor will also provide the message of the moving average power dissipation of the circuit under test to the on-line scheduler. As for the on-line powerconstrained scheduler, the integrator circuitry will translate the voltage message to measured average power dissipation and pass to a comparator. When the power is over-dissipated, the arbiter will lower the test frequency or let one of the core tests stop for a proper duration. The architecture will promote the defect coverage owing to combining BISTs with IDDQ tests, survive the IDDQ test due to the low-voltage design, protect the SOC under test by arranging the core tests according to the monitored message of the moving average power dissipation.
本計畫以現有技術設計一個單一電源可低於PN 兩臨界電壓和的低電壓電路，此電流感測器之電流感測電晶體亦將電源電流轉換為電壓訊號提供即時低功率測試排程控制器之用。在即時低功率測試排程控制器部分，將會由此待測電路電壓經由電流積分器反應出在一段時間內之平均功率，此功率與參考值比較，當功率過高時，仲裁器將會以測試頻率降低或命令其中一個核心電路暫停測試的方式來降低平均功率。此架構將藉由邏輯測試與電流測試提高缺陷涵蓋率；藉由低電壓設計使電流測試法繼續適用於深次微米電路中；繼而藉由電流感測器提供平均功率的訊息，用以降低測試時過高功率消耗而造成系統晶片毀損的危險。另外，我們也完成了混合排程與排程的演算法，由模擬證實，此法適用於低功率平行測試中。 |
| 關聯: | 國科會計畫, 計畫編號: NSC91-2215-E235-001; 研究期間: 9108-9207 |
| 顯示於類別: | [電子工程學系] 國科會計畫
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