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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19100

Title: Combination of Automatic Test Pattern Generation and Built-in Intermediate Voltage Sensing for Detecting CMOS Bridging Faults
Authors: Lee, Kuen-Jong;Tang, Jing-Jou;Huang, Tsung-Chu;Tsai, Cheng-Liang
Contributors: 電子工程學系
Date: 1996
Issue Date: 2014-10-27T08:08:00Z
Abstract: This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intemediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.
Relation: Proceedings of the 1996 5th Asian Test Symposium, ATS'96, : 100-105
Appears in Collections:[電子工程學系] 會議論文

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