This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intemediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.
Proceedings of the 1996 5th Asian Test Symposium, ATS'96, : 100-105