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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/19103
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| Title: | An Input Control Technique for Power Reduction in Scan Circuits During Test Application |
| Authors: | Huang, Tsung-Chu;Lee, Kuen-Jong |
| Contributors: | 電子工程學系 |
| Date: | 1999
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| Issue Date: | 2014-10-27T08:08:04Z
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| Abstract: | This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques. |
| Relation: | Proceedings of the 1999 8th Asian Test Symposium (ATS'99), : 315-320 |
| Appears in Collections: | [電子工程學系] 會議論文
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