National Changhua University of Education Institutional Repository : Item 987654321/19103
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题名: An Input Control Technique for Power Reduction in Scan Circuits During Test Application
作者: Huang, Tsung-Chu;Lee, Kuen-Jong
贡献者: 電子工程學系
日期: 1999
上传时间: 2014-10-27T08:08:04Z
摘要: This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.
關聯: Proceedings of the 1999 8th Asian Test Symposium (ATS'99), : 315-320
显示于类别:[電子工程學系] 會議論文

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