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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19106

Title: A Low-Power LFSR Architecture
Authors: Huang, Tsung-Chu;Lee, Kuen-Jong
Contributors: 電子工程學系
Date: 2001
Issue Date: 2014-10-27T08:08:07Z
Abstract: LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.
Relation: Proceedings of the 10th Asian Test Symposium, : 470
Appears in Collections:[電子工程學系] 會議論文

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