National Changhua University of Education Institutional Repository : Item 987654321/19106
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 6507/11669
造访人次 : 30697224      在线人数 : 252
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 进阶搜寻


题名: A Low-Power LFSR Architecture
作者: Huang, Tsung-Chu;Lee, Kuen-Jong
贡献者: 電子工程學系
日期: 2001
上传时间: 2014-10-27T08:08:07Z
摘要: LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.
關聯: Proceedings of the 10th Asian Test Symposium, : 470
显示于类别:[電子工程學系] 會議論文


档案 大小格式浏览次数



DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈