National Changhua University of Education Institutional Repository : Item 987654321/19106
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题名: A Low-Power LFSR Architecture
作者: Huang, Tsung-Chu;Lee, Kuen-Jong
贡献者: 電子工程學系
日期: 2001
上传时间: 2014-10-27T08:08:07Z
摘要: LFSRs are widely used in Built-In Self-Test (BIST) environment. A multiphase technique proposed to reduce the data transitions (DTs) in both the LFSR and the circuit under test has been found to have some limitations. This paper discusses the development of a low-power multiphase clock generator and the employment of static demultiplexers. It also proposes a hybrid design to reduce the power.
關聯: Proceedings of the 10th Asian Test Symposium, : 470
显示于类别:[電子工程學系] 會議論文

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