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Title: A Supply-Gating Scheme for Both Data-Retention and Spike-Reduction in Power Management and Test Scheduling
Authors: Huang, Tsung-Chu;Tzeng, Jing-Chi;Chao, Yuan-Wei;Chen, Ji-Jan;Liu, Wei-Ting;Lee, Kuen-Jong
Contributors: 電子工程學系
Date: 2006-04
Issue Date: 2014-10-27T08:08:10Z
Publisher: IEEE
Abstract: Power gating using sleep transistors is a trend for power management and test scheduling in the deep-submicron and even nanometer resolutions. This paper develops a sleep transistor allocation structure that can not only reduce the spike-time product with data retention but also balance the noise margins and timing in active mode. A switching activity based model is developed as a heuristics for sleep transistor clustering. Under the proposed model, the spike reduction can be up to 83% in average
Relation: 2006 International Symposium on VLSI Design, Automation and Test(VLSI-DAT), : 167-170
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