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http://ir.ncue.edu.tw/ir/handle/987654321/19112
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| 題名: | Congruence Synchronous Mirror Delay |
| 作者: | Huang, Tsung-Chu;Chang, Gau-Bin;Li, Ling |
| 貢獻者: | 電子工程學系 |
| 日期: | 2007-05
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| 上傳時間: | 2014-10-27T08:08:12Z
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| 出版者: | IEEE |
| 摘要: | Digital synchronous mirror delaylines can lock in only two cycles and make burst and sleep modes feasible for high-speed and low-power applications. Conventional digital synchronous mirror delay usually spends at least one delay line with a length comparable to the resolution. The area overhead becomes an issue in multiple-module circuits. The objective of this paper is thus to reduce the area overhead by folding the delayline. Simple corollaries from the congruence theorem are derived for function proves. Experimental results show that the proposed design can save more than 75% of area overhead for fixed skew compensation of hundreds of stages under acceptable phase errors. |
| 關聯: | IEEE International Symposium on Circuits and Systems (ISCAS 2007), : 2184-2187 |
| 顯示於類別: | [電子工程學系] 會議論文
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