English  |  正體中文  |  简体中文  |  Items with full text/Total items : 6491/11663
Visitors : 24488586      Online Users : 67
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search
LoginUploadHelpAboutAdminister

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19116

Title: Power-Gating Current Test for Static RAM in Nanotechnologies
Authors: Chao, Yuan-Wei;Chen, Hsin-Ling;Chen, Chih-Jong;Huang, Tsung-Chu
Contributors: 電子工程學系
Date: 2007-12
Issue Date: 2014-10-27T08:08:26Z
Publisher: IEEE
Abstract: Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.
Relation: IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2007), : 42-45
Appears in Collections:[電子工程學系] 會議論文

Files in This Item:

File SizeFormat
index.html0KbHTML395View/Open


All items in NCUEIR are protected by copyright, with all rights reserved.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback