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題名: Power-Gating Current Test for Static RAM in Nanotechnologies
作者: Chao, Yuan-Wei;Chen, Hsin-Ling;Chen, Chih-Jong;Huang, Tsung-Chu
貢獻者: 電子工程學系
日期: 2007-12
上傳時間: 2014-10-27T08:08:26Z
出版者: IEEE
摘要: Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced.
關聯: IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2007), : 42-45
顯示於類別:[電子工程學系] 會議論文


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