National Changhua University of Education Institutional Repository : Item 987654321/19121

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NCUEIR > College of Engineering > eedept > Proceedings > Item 987654321/19121

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19121

Title:	Area-Efficient True One-Period Delayline for Cycle-to-Cycle Jitter Measurement
Authors:	Yang, Cheng-Han;Chou, Yi-Hsian;Huang, Tsung-Chu
Contributors:	電子工程學系
Date:	2008-08
Issue Date:	2014-10-27T08:08:30Z
Publisher:	國立交通大學
Relation:	The 19th VLSI Design/CAD Symposium, : 280-283
Appears in Collections:	[eedept] Proceedings

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