National Changhua University of Education Institutional Repository : Item 987654321/19128
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 6507/11669
造访人次 : 29944371      在线人数 : 456
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
搜寻范围 进阶搜寻

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://ir.ncue.edu.tw/ir/handle/987654321/19128

题名: Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency
作者: Hsu, Wei-Ning;Wu, Tsu-Hsin;Huang, Tsung-Chu
贡献者: 電子工程學系
日期: 2009
上传时间: 2014-10-27T08:08:36Z
出版者: IEEE
摘要: Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.
關聯: Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), : 38-43
显示于类别:[電子工程學系] 會議論文

文件中的档案:

档案 大小格式浏览次数
index.html0KbHTML517检视/开启


在NCUEIR中所有的数据项都受到原著作权保护.

 

DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 回馈