National Changhua University of Education Institutional Repository : Item 987654321/19128
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題名: Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency
作者: Hsu, Wei-Ning;Wu, Tsu-Hsin;Huang, Tsung-Chu
貢獻者: 電子工程學系
日期: 2009
上傳時間: 2014-10-27T08:08:36Z
出版者: IEEE
摘要: Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content addressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of postlayout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.
關聯: Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), : 38-43
顯示於類別:[電子工程學系] 會議論文

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