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Items for Author "Kao, Tzi-Wei" 

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CollectionDateTitleAuthors
[電子工程學系] 期刊論文 2010-12 Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs Wu, Tsung-Yi; Kao, Tzi-Wei; Lin, How-Rern
[電子工程學系] 會議論文 2010-01 Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC Designs Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern
[電子工程學系] 會議論文 2009-05 A Peak Current and Power Pad Count Reduction Tool for System-Level IC Designers Wu, Tsung-Yi; Kao, Tzi-Wei; Huang, Shi-Yi; Li, Tai-Lun; Lin, How-Rern

 


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