National Changhua University of Education Institutional Repository : Item 987654321/10256
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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/10256

Title: Hardware Implementation for a Genetic Algorithm
Authors: Chen, Pei-Yin;Chen, Ren-Der;Chang, Yu-Pin;Shieh, Leang-San;Malki, Heidar A.
Contributors: 資訊工程學系
Keywords: Field-programmable gate array (FPGA);Genetic algorithm (GA);Intellectual property (IP);Software system;Verilog
Date: 2008-04
Issue Date: 2012-05-22T06:12:25Z
Publisher: Institute of Electrical and Electronics Engineers
Abstract: A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.
Relation: IEEE Trans. Instrumentation and Measurement, 57(4): 699-705
Appears in Collections:[Department and Graduate Institute of Computer Science and Information Engineering] Periodical Articles

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