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Please use this identifier to cite or link to this item:
http://ir.ncue.edu.tw/ir/handle/987654321/10385
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| Title: | Comparison of Two Data Hazard Handling Schemes for Asynchronous Pipelined Processors |
| Authors: | Chang, Meng-chou;Shiau, Da-Sen |
| Contributors: | 電子工程學系 |
| Keywords: | Asynchronous logic;Pipelined processor;Data hazard;Data hazard detection table |
| Date: | 2010-07
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| Issue Date: | 2012-05-22T06:47:40Z
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| Publisher: | IEEE |
| Abstract: | Since asynchronous logic adopts a distributed
control scheme, the traditional methods for handling hazards
in synchronous processors cannot be directly applied to
asynchronous processors. Recently, the data hazard detection
table (DHDT) scheme has been regarded as an effective
method for handling data hazards in asynchronous processors.
In this paper, two asynchronous data hazard handling schemes,
the DHDT scheme and the proposed destination register chain
(DRC) scheme, are compared in terms of performance and
hardware complexity. In order to evaluate these two data
hazard handling schemes, we have used the Balsa
asynchronous synthesis system to implement two asynchronous
pipelined processors, AsynRISC-DHDT and AsynRISC-DRC,
which employ DHDT and DRC, respectively, to deal with data
hazards. Experimental results show that AsynRISC-DRC can
achieve a 13% reduction in hardware area cost and a
performance gain of22 .1% compared with AsynRISC-DHDT. |
| Relation: | The 3rd IEEE International Conference on Computer Science and Information Technology, 2010年7月9-11日, v4: 36-40 |
| Appears in Collections: | [電子工程學系] 會議論文
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