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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/11660

Title: Low Test-Application Time Method for EEPLA testing
Authors: Wei, Kai-Cheng;Liu, B. D.;Tang, J. J.
Contributors: 資訊工程系
Date: 1997-01
Issue Date: 2012-06-18T02:34:29Z
Publisher: Institute of Electrical Engineers
Abstract: An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.
Relation: EE Proc. Computer and Digital Techniques, 144(1): 39-42
Appears in Collections:[資訊工程學系] 期刊論文

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