National Changhua University of Education Institutional Repository : Item 987654321/14027

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NCUEIR > College of Engineering > eedept > Proceedings > Item 987654321/14027

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/14027

Title:	A VLSI Design with Built-in SRAM Arrays for Implementing Full Search Block Matching Algorithm
Authors:	Wu, Tsung-Yi;Chen, Kuang-Yao;Huang, Shi-Yi;Li, Tai-Lun;Lin, How-Rern
Contributors:	電子工程學系
Keywords:	Full search block matching algorithm;2-D systolic PE array;Motion estimation
Date:	2009-05
Issue Date:	2012-09-10T02:55:57Z
Publisher:	Institute of Electrical and Electronics Engineers
Abstract:	A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to store a current frame, a reference frame, and a prefetch frame. Our chip only needs 8 input pads to read off-chip image data. Experimental results show that our proposed chip can process 704 frames per second for the CIF format. By extending the SRAM arrays, our proposed chip can process 34 frames per second for the HDTV resolution.
Relation:	The 13th IEEE International Symposium on Consumer Electronics, ISCE 2009, Kyoto, May 25-28, 2009: 619-621
Appears in Collections:	[eedept] Proceedings

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