English  |  正體中文  |  简体中文  |  Items with full text/Total items : 6481/11653
Visitors : 22666598      Online Users : 176
RC Version 3.2 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Adv. Search
LoginUploadHelpAboutAdminister

Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/1734

Title: A Multiplier Based on the Algorithm of Chinese Abacus
Authors: Lin, C.-H.;Yi, S.-C.;Chen, J.-J.
Contributors: 積體電路設計研究所
Keywords: Braun Array Multiplier
Chinese Abacus Multiplier
Fast Multiplier
Date: 2009-01
Issue Date: 2010-11-12T07:21:50Z
Abstract: A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus
multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multiplier is, respectively, less about 11.9% and 22.3% also.
Relation: WSEAS Transactions on Electronics, 6(1), 2009:11-22
Appears in Collections:[積體電路設計研究所] 期刊論文

Files in This Item:

File SizeFormat
index.html0KbHTML679View/Open


All items in NCUEIR are protected by copyright, with all rights reserved.

 


DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback