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Please use this identifier to cite or link to this item: http://ir.ncue.edu.tw/ir/handle/987654321/19082

Title: Token Scan Cell for Low Power Testing
Authors: Huang, Tsung-Chu;Lee, Kuen-Jong
Contributors: 電子工程學系 
Date: 2001-05
Issue Date: 2014-10-27T08:06:18Z
Publisher: Institution of Engineering and Technology
Abstract: A multiphase clocking technique is presented for reducing the test power for scan-based circuits. A novel scan cell design called the token scan cell is developed, which combines a phase-generating flip-flop and a data flip-flop to overcome the inter-phase skew and clock routing problems. Experimental results show that on average ∼87% of the data transition count during scanning is reduced. For many circuits with long chains, a reduction of >98% can even be achieved.
Relation: Electronics Letters, 37(11): 678-679
Appears in Collections:[eedept] Periodical Articles

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